In processes of 65 nm technology node and below, in order to reduce the resistance and the parasitic depletion-region capacitance of a polysilicon gate and thereby to improve the overall performance of the device, part of the polysilicon gate is usually doped with a certain amount of dopant ions and thereby the polysilicon gate is formed into a composite structure consisting of a doped upper portion and an undoped lower portion. However, in such structure, affected by the existence of the dopant ions, the doped portion has an etching rate higher than that of the undoped portion even under the same etching and cleaning conditions, which leads to different profiles between the doped portion and undoped portion after etch, as shown in FIG. 1, wherein an etched doped portion 104 and an etched undoped portion 103 are formed on a gate oxide layer 102 that is formed on a semiconductor substrate 101, and the etched doped portion 104 has a smaller width than that of the etched undoped portion 103 (as indicated by the area of the figure marked with an oblong). Such profile difference will lead to a gate with an unsatisfying profile and a relatively large deviation in size which will affect the overall performance of the device.
A method for etching polysilicon gate of the prior art developed for solving the above issue of different profiles between the etched doped and undoped portions includes the following steps of:
manually measuring the thickness of the doped polysilicon portion according to an analytical image of a cross section obtained by using cross-section analysis means, e.g., a transmission electron microscopy (TEM);
etching the doped and undoped polysilicon portions in two respective steps with different parameters; and
defining different etching times, which will be kept constant in subsequent etching processes, respectively for the two portions according to a formula based on the above measured thicknesses of both the doped and undoped polysilicon portions.
Nevertheless, this method has drawbacks as follows:
First, errors will be inevitably generated in manual thickness measurement for the doped polysilicon portion.
Second, the result obtained from a limited number of samples (generally 1 or 2 samples) may not work for wafers of different lots, as wafer characteristics vary with lot in growth and doping conditions.
Third, the etching time is fixed and would not be adjusted for any single wafer according to its growth or doping condition.
Therefore, the method for etching polysilicon gate of the prior art is lack of universality in addressing the issue of different profiles between etched doped portion and undoped portion of a polysilicon gate.
Thus, there is a need to improve the existing method for etching polysilicon gate so as to effectively increase the profile consistency between the etched doped portion and undoped portion of a polysilicon gate.